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| the m pd75p3116 replaces the m pd753108s internal mask rom with a one-time prom, and features expanded rom capacity. because the m pd75p3116 supports programming by users, it is suitable for use in evaluation of systems in the development stage using the m pd753104, 753106, or 753108, and for use in small-scale production. detailed information about functions is provided in the following users manual. be sure to read it before designing: m pd753108 users manual : u10890e features compatible with m pd753108 memory capacity: ? prom : 16384 x 8 bits ? ram : 512 x 4 bits can be operated in same power supply voltage range as the mask version m pd753108 ? v dd = 1.8 to 5.5 v on-chip lcd controller/driver qtop tm microcontroller remark qtop microcontrollers are microcontrollers with on-chip one-time prom that are totally supported by nec. the support include writing application programs, marking, screening, and verification. ordering information part number package m pd75p3116gc-ab8 64-pin plastic qfp (14 x 14 mm, 0.8-mm pitch) m pd75p3116gk-8a8 64-pin plastic qfp (12 x 12 mm, 0.65-mm pitch) caution this device does not provide an internal pull-up resistor connection function by means of mask option. m pd75p3116 mos integrated circuit 4-bit single-chip microcontroller the mark shows major revised points. document no. u11369ej2v0ds00 (2nd edition) date published march 1997 n printed in japan 1994 data sheet the information in this document is subject to change without notice.
m pd75p3116 2 function outline item function instruction execution time ? 0.95, 1.91, 3.81, or 15.3 m s (main system clock: @ 4.19 mhz) ? 0.67, 1.33, 2.67, or 10.7 m s (main system clock: @ 6.0 mhz) ? 122 m s (subsystem clock: @ 32.768 khz) internal memory prom 16384 x 8 bits ram 512 x 4 bits general-purpose register ? 4-bit manipulation: 8 x 4 banks ? 8-bit manipulation: 4 x 4 banks i/o ports cmos input 8 internal pull-up resistor connection can be specified by software: 7 cmos i/o 20 internal pull-up resistor connection can be specified by software: 12 shared by segment pin: 8 n-ch open-drain i/o 4 13-v withstand voltage total 32 lcd controller/driver ? segment number selection : 16/20/24 segments (switchable to cmos i/o ports in a batch of 4 pins, max. 8 pins) ? display mode selection : static, 1/2 duty (1/2 bias), 1/3 duty (1/2 bias), 1/3 duty (1/3 bias), 1/4 duty (1/3 bias) timers 5 channels: ? 8-bit timer/event counter : 3 channels (can be used as 16-bit timer/event counter, carrier generator, and timer with gate) ? basic interval timer/watchdog timer : 1 channel ? watch timer : 1 channel serial interface ? 3-wire serial i/o mode msb/lsb first switchable ? 2-wire serial i/o mode ? sbi mode bit sequential buffer (bsb) 16 bits clock output (pcl) f , 524, 262, and 65.5 khz (main system clock: @ 4.19 mhz) f , 750, 375, and 93.8 khz (main system clock: @ 6.0 mhz) buzzer output (buz) ? 2, 4, and 32 khz ( main system clock: @ 4.19 mhz or subsystem clock: @ 32.768 khz ) ? 2.93, 5.86, 46.9 khz (main system clock: @ 6.0 mhz) vectored interrupts ? external : 3 ? internal : 5 test inputs ? external : 1 ? internal : 1 system clock oscillation circuit ? ceramic/crystal oscillation circuit for main system clock ? crystal oscillation circuit for subsystem clock standby function stop/halt mode power supply voltage v dd = 1.8 to 5.5 v package ? 64-pin plastic qfp (14 x 14 mm, 0.8-mm pitch) ? 64-pin plastic qfp (12 x 12 mm, 0.65-mm pitch) m pd75p3116 3 contents 1. pin configuration (top view) .................................................................................................. 4 2. block diagram ............................................................................................................................ 5 3. pin functions ............................................................................................................................... 6 3.1 port pins ................................................................................................................................................... 6 3.2 non-port pins ........................................................................................................................................... 8 3.3 equivalent circuits for pins .................................................................................................................... 10 3.4 recommended connection of unused pins ......................................................................................... 12 4. mk i and mk ii mode selection function ............................................................................. 13 4.1 differences between mk i mode and mk ii mode ................................................................................... 13 4.2 setting of stack bank selection (sbs) register ................................................................................... 14 5. differences between m pd75p3116 and m pd753104, 753106, and 753108 ...................... 15 6. memory configuration ........................................................................................................... 16 7. instruction set .......................................................................................................................... 18 8. one-time prom (program memory) write and verify ................................................... 27 8.1 operation modes for program memory write/verify ............................................................................ 27 8.2 program memory write procedure ......................................................................................................... 28 8.3 program memory read procedure ......................................................................................................... 29 8.4 one-time prom screening ..................................................................................................................... 30 9. electrical specifications ..................................................................................................... 31 10. characteristic curves (reference values) .................................................................. 46 11. package drawings ................................................................................................................... 48 12. recommended soldering conditions ................................................................................ 50 appendix a. function list of m pd75308b, 753108, and 75p3116 ........................................... 51 appendix b. development tools ................................................................................................ 53 appendix c. related documents ............................................................................................... 57 m pd75p3116 4 1. pin configuration (top view) ? 64-pin plastic qfp (14 x 14 mm, 0.8-mm pitch) : m pd75p3116gc-ab8 ? 64-pin plastic qfp (12 x 12 mm, 0.65-mm pitch) : m pd75p3116gk-8a8 note always connect the v pp pin directly to v dd during normal operation. pin identifications p00-p03 : port0 com0 to com3 : common output 0 to 3 p10-p13 : port1 v lc0 to v lc2 : lcd power supply 0 to 2 p20-p23 : port2 bias : lcd power supply bias control p30-p33 : port3 lcdcl : lcd clock p50-p53 : port5 sync : lcd synchronization p60-p63 : port6 ti0 to ti2 : timer input 0 to 2 p80-p83 : port8 pto0 to pto2 : programmable timer output 0 to 2 p90-p93 : port9 buz : buzzer clock kr0-kr3 : key return 0 to 3 pcl : programmable clock sck : serial clock int0, 1, 4 : external vectored interrupt 0, 1, 4 si : serial input int2 : external test input 2 so : serial output x1, x2 : main system clock oscillation 1, 2 sb0, sb1 : serial data bus 0, 1 xt1, xt2 : subsystem clock oscillation 1, 2 reset : reset v pp : programming power supply md0 to md3 : mode selection 0 to 3 v dd : positive power supply d0 to d7 : data bus 0 to 7 vss : ground s0 to s23 : segment output 0 to 23 48 s12 47 s13 46 s14 45 s15 44 p93/s16 43 p92/s17 42 p91/s18 41 p90/s19 40 p83/s20 39 p82/s21 38 p81/s22 37 p80/s23 36 p23/buz 35 p22/pcl/pto2 34 p21/pto1 33 p20/pto0 64 com3 63 com2 62 com1 61 com0 60 s0 59 s1 58 s2 57 s3 56 s4 55 s5 54 s6 53 s7 52 s8 51 s9 50 s10 49 s11 1 bias 2 v lc0 3 v lc1 4 v lc2 5 p30/lcdcl/md0 6 p31/sync/md1 7 p32/md2 8 p33/md3 9 vss 10 p50/d4 11 p51/d5 12 p52/d6 13 p53/d7 14 p60/kr0/d0 15 p61/kr1/d1 16 p62/kr2/d2 17 p63/kr3/d3 18 reset 19 xt1 20 xt2 21 v pp 22 x1 23 x2 24 v dd 25 p00/int4 26 p01/sck 27 p02/so/sb0 28 p03/si/sb1 29 p10/int0 30 p11/int1 31 p12/int2/ti1/ti2 32 p13/ti0 note m pd75p3116 5 2. block diagram p20 to p23 port0 p00 to p03 s0 to s15 16 4 4 4 4 4 4 4 4 com0 to com3 4 bias f lcd v pp v dd reset vss cpu clock f stand by control x2 x1 xt2 xt1 system clock generator main sub clock divider clock output control fx/2 n pcl/pto2/p22 general reg. data memory (ram) 512 x 4 bits bank sbs sp (8) cy alu program counter (14) program memory (prom) 16384 x 8 bits decode and control port1 p10 to p13 port2 port3 p30/md0 to p33/md3 port5 p50/d4 to p53/d7 port6 p60/d0 to p63/d3 port8 p80 to p83 port9 p90 to p93 lcd controller/ driver 4 s16/p93 to s19/p90 4 s20/p83 to s23/p80 v lc0 v lc1 v lc2 sync/p31 lcdcl/p30 clocked serial interface si/sb1/p03 intcsi interrupt control int0/p10 so/sb0/p02 sck/p01 tout0 int1/p11 int4/p00 int2/p12/ti1/ti2 p60/kr0 to p63/kr3 bit seq. buffer (16) 4 int1 8-bit timer/event counter #1 8-bit timer/event counter #2 cascaded 16-bit timer/ event counter intt2 intt1 ti1/ti2/ p12/int2 pto1/p21 tout0 pto2/ pcl/p22 intt0 tout0 8-bit timer/event counter #0 ti0/p13 pto0/p20 basic interval timer/ watchdog timer intbt buz/p23 watch timer intw f lcd m pd75p3116 6 3. pin functions 3.1 port pins (1/2) pin name i/o alternate function function 8-bit status i/o circuit i/o after reset type note 1 p00 input int4 4-bit input port (port0) x input p01 to p03 are 3-bit pins for which connection of p01 i/o sck an internal pull-up resistor can be specified by m pd75p3116 7 3.1 port pins (2/2) pin name i/o alternate function function 8-bit status i/o circuit i/o after reset type note 1 p60 i/o kr0/d0 programmable 4-bit i/o port (port6) x input m pd75p3116 8 3.2 non-port pins (1/2) pin name i/o alternate function function status i/o circuit after reset type note 1 ti0 input p13 external event pulse input to timer/event counter input -c ti1 p12/int2/ti2 ti2 p12/int2/ti1 pto0 output p20 timer/event counter output input e-b pto1 p21 pto2 p22/pcl pcl p22/pto2 clock output buz p23 frequency output (for buzzer or system clock trimming) sck i/o p01 serial clock i/o input m pd75p3116 9 3.2 non-port pins (2/2) pin name i/o alternate function function status i/o circuit after reset type s0 to s15 output segment signal output note 1 g-a s16 to s19 output p93 to p90 segment signal output input h s20 to s23 output p83 to p80 segment signal output input h com0 to com3 output common signal output note 1 g-b v lc0 to v lc2 power supply for driving lcd bias output output for external split resistor cut note 2 lcdcl note 3 i/o p30/md0 clock output for driving external expansion driver input e-b sync note 3 i/o p31/md1 clock output for synchronization of external expansion driver input e-b notes 1. the v pp pin does not operate normally if it is not connected with v dd pin when normal operation. 2. the v lcx (x = 0, 1, 2) shown below are selected as the input source for the display outputs. s0 to s23: v lc1 , com0 to com2: v lc2 , com3: v lc0 3. when the split resistor is incorporated : low level when the split resistor is not incorporated : high impedance 4. these pins are provided for future system expansion. currently, only p30 and p31 are used. m pd75p3116 10 3.3 equivalent circuits for pins the equivalent circuits for the m pd75p3116s pins are shown in abbreviated form below. in v dd p-ch n-ch v dd p-ch n-ch out data output disable in v dd p-ch in/out p.u.r. enable data p.u.r. type d output disable p.u.r. : pull-up resistor type a v dd p-ch p.u.r. enable p.u.r. p.u.r. : pull-up resistor in v dd p-ch in/out p.u.r. enable data p.u.r. type d output disable p.u.r. : pull-up resistor type b cmos standard input buffer push-pull output that can be set to high impedance output (with both p-ch and n-ch off). schmitt trigger input with hysteresis characteristics. (continued) type a type d type e-b type b type b-c type f-a m pd75p3116 11 (continued) type f-b type h type m-c type g-a type g-b type m-e output disable v dd p-ch n-ch in/out data v dd p-ch p.u.r. enable p.u.r. output disable (n) output disable (p) p.u.r. : pull-up resistor in/out type g-a type e-b seg data output disable data v dd p-ch in/out p.u.r. enable data p.u.r. output disable p.u.r. : pull-up resistor n-ch pull-up resistor that operates only when an input instruction is executed. (the current flows from v dd to a pin when the pin is at low level.) note out n-ch p-ch n-ch p-ch n-ch p-ch n-ch p-ch n-ch p-ch n-ch n-ch v lc0 v lc1 seg data v lc2 n-ch p-ch p-ch n-ch n-ch n-ch p-ch p-ch n-ch out v lc0 v lc1 v lc2 com data voltage controller output disable data n-ch in/out (+13-v withstand voltage) v dd p-ch input instruction note p.u.r. (+13-v withstand voltage) p-ch n-ch m pd75p3116 12 3.4 recommended connection of unused pins table 3-1. list of unused pin connection pin recommended connection p00/int4 connect to vss or v dd p01/sck individually connect to vss or v dd through a resistor. p02/so/sb0 p03/si/sb1 connect to vss p10/int0 and p11/int1 connect to vss or v dd p12/ti1/ti2/int2 p13/ti0 p20/pto0 input status : individually connect to vss or v dd p21/pto1 through a resistor p22/pto2/pcl output status : leave open p23/buz p30/lcdcl/md0 p31/sync/md1 p32/md2 p33/md3 p50/d4 to p53/d7 connect to vss p60/kr0/d0 to p63/kr3/d3 input status : individually connect to vss or v dd through a resistor output status : leave open s0 to s15 leave open com0 to com3 s16/p93 to s19/p90 input status : individually connect to vss or v dd through a resistor s20/p83 to s23/p80 output status : leave open v lc0 to v lc2 connect to vss bias connect to vss only when neither of v lc0 , v lc1 and v lc2 is used. in other cases, leave open. xt1 note connect to vss or v dd xt2 note leave open v pp always connect to v dd directly note in case the subsystem clock is not used, set sos.0 = 1 (on-chip feedback resistor not used). m pd75p3116 13 4. mk i and mk ii mode selection function setting a stack bank selection (sbs) register for the m pd75p3116 enables the program memory to be switched between the mk i mode and mk ii mode. this function is applicable when using the m pd75p3116 to evaluate the m pd753104, 753106, or 753108. when the sbs bit 3 is set to 1 : sets the mk i mode (supports the mk i mode for the m pd753104, 753106, and 753108) when the sbs bit 3 is set to 0 : sets the mk ii mode (supports the mk ii mode for the m pd753104, 753106, and 753108) 4.1 differences between mk i mode and mk ii mode table 4-1 lists differences between the mk i mode and the mk ii mode for the m pd75p3116. table 4-1. differences between mk i mode and mk ii mode item mk i mode mk ii mode program counter pc 13-0 program memory (bytes) 16384 data memory (bits) 512 x 4 stack stack bank selectable via memory banks 0, 1 no. of stack bytes 2 bytes 3 bytes instruction bra !addr1 instruction not available available calla !addr1 instruction instruction call !addr instruction 3 machine cycles 4 machine cycles execution time callf !faddr instruction 2 machine cycles 3 machine cycles supported mask roms when set to mk i mode: when set to mk ii mode: m pd753104, 753106, and 753108 m pd753104, 753106, and 753108 caution the mk ii mode supports a program area exceeding 16 kbytes for the 75x and 75xl series. therefore, this mode is effective for enhancing software compatibility with products that have a program area of more than 16 kbytes. with regard to the number of stack bytes during execution of subroutine call instructions, the usable area increases by 1 byte per stack compared to the mk i mode when the mk ii mode is selected. however, when the call !addr and callf !faddr instructions are used, the machine cycle becomes longer by 1 machine cycle. therefore, if more emphasis is placed on ram use efficiency and processing performance than on software compatibility, the mk i mode should be used. m pd75p3116 14 4.2 setting of stack bank selection (sbs) register use the stack bank selection register to switch between the mk i mode and mk ii mode. figure 4-1 shows the format of the stack bank selection register. the stack bank selection register is set using a 4-bit memory manipulation instruction. when using the mk i mode, be sure to initialize the stack bank selection register to 100xb note at the beginning of the program. when using the mk ii mode, be sure to initialize it to 000xb note . note set the desired value for x. figure 4-1. format of stack bank selection register caution sbs3 is set to 1 after reset input, and consequently the cpu operates in the mk i mode. when using instructions for the mk ii mode, set sbs3 to 0 and set the mk ii mode before using the instructions. sbs3 sbs2 sbs1 sbs0 f84h address 3 2 1 0 sbs 0 0 1 1 0 1 0 1 symbol stack area specification memory bank 0 memory bank 1 setting prohibited 0 be sure to enter ? for bit 2. 0 1 mk ii mode mk i mode mode selection specification m pd75p3116 15 5. differences between m pd75p3116 and m pd753104, 753106, 753108 the m pd75p3116 replaces the internal mask rom in the m pd753104, 753106, and 753108 with a one-time prom and features expanded rom capacity. the m pd75p3116s mk i mode supports the mk i mode in the m pd753104, 753106, and 753108 and the m pd75p3116s mk ii mode supports the mk ii mode in the m pd753104, 753106, and 753108. table 5-1 lists differences among the m pd75p3116 and the m pd753104, 753106, and 753108. be sure to check the differences among these products before using them with proms for debugging or prototype testing of application systems or, later, when using them with a mask rom for full-scale production. for details on the cpu functions and internal hardware, refer to the users manual . table 5-1. differences between m pd75p3116 and m pd753104, 753106, and 753108 item m pd753104 m pd753106 m pd753108 m pd75p3116 program counter 12 bits 13 bits 14 bits program memory (bytes) mask rom mask rom mask rom one-time prom 4096 6144 8192 16384 data memory (x 4 bits) 512 mask options pull-up resistor for available not available port5 (on chip/not on chip can be specified.) (not on chip) split resistor for lcd driving power supply wait time after available not available reset (selectable between 2 17 /f x and 2 15 /f x ) (fixed to 2 15 /f x ) note feedback resistor available not available of subsystem clock (use/not use can be selected.) (enable) pin configuration pin nos. 5 to 8 p30 to p33 p30/md0 to p33/md3 pin nos. 10 to 13 p50 to p53 p50/d4 to p53/d7 pin nos. 14 to 17 p60/kr0 to p63/kr3 p60/kr0/d0 to p63/kr3/d3 pin no. 21 ic v pp other noise resistance and noise radiation may differ due to the different circuit sizes and mask layouts. note 2 17 /f x : 21.8 ms at 6.0-mhz operation, 31.3 ms at 4.19-mhz operation 2 15 /f x : 5.46 ms at 6.0-mhz operation, 7.81 ms at 4.19-mhz operation caution noise resistance and noise radiation are different in prom and mask roms. when changing from prom versions to mask rom versions when switching from prototype development to full production, be sure to fully evaluate the mask rom versions cs (not es). m pd75p3116 16 6. memory configuration figure 6-1. program memory map note can be used only in the mk ii mode remark for instructions other than those noted above, the br pcde and br pcxa instructions can be used to branch to addresses with changes in the pcs lower 8 bits only. mbe mbe mbe mbe mbe mbe mbe rbe rbe rbe rbe rbe rbe rbe internal reset start address (upper 6 bits) internal reset start address (lower 8 bits) intbt/int4 start address (upper 6 bits) intbt/int4 start address (lower 8 bits) int0 start address (upper 6 bits) int0 start address (lower 8 bits) int1 start address (upper 6 bits) int1 start address (lower 8 bits) intcsi start address (upper 6 bits) intcsi start address (lower 8 bits) intt0 start address (upper 6 bits) intt0 start address (lower 8 bits) intt1/intt2 start address (upper 6 bits) intt1/intt2 start address (lower 8 bits) reference table for geti instruction 0000h 0002h 0004h 0006h 0008h 000ah 000ch 0020h 007fh 0080h 07ffh 0800h 0fffh 1000h 1fffh 2000h 2fffh 3000h 3fffh callf !faddr instruction entry address branch addresses for the following instructions ?br !addr ?call !addr ?bra !addr1 ?calla !addr1 ?br bcde ?br bcxa branch/call address by geti br $addr instruction relative branch address (?5 to ?, +2 to +16) brcb !caddr instruction branch address brcb !caddr instruction branch address brcb !caddr instruction branch address brcb !caddr instruction branch address 765 0 note note m pd75p3116 17 figure 6-2. data memory map note memory bank 0 or 1 can be selected as the stack area. (32 x 4) 256 x 4 (224 x 4) 128 x 4 0 1 15 000h 01fh 020h 0ffh 100h 1e0h 1dfh 1f7h 1f8h f80h fffh general-purpose register area display data memory data area static ram (512 x 4) stack area note peripheral hardware area data memory memory bank not incorporated 1ffh 256 x 4 (224 x 4) (24 x 4) (8 x 4) m pd75p3116 18 7. instruction set (1) representation and coding formats for operands in the instructions operand area, use the following coding format to describe operands corresponding to the instructions operand representations (for further description, refer to the ra75x assembler package users manual language (eeu-1363) ). when there are several codes, select and use just one. codes that consist of upper-case letters and + or C symbols are key words that should be entered as they are. for immediate data, enter an appropriate numerical value or label. enter register flag symbols as label descriptors instead of mem, fmem, pmem, bit, etc. (for further description, refer to the users manual ). the number of labels that can be entered for fmem and pmem are restricted. representation coding format reg x, a, b, c, d, e, h, l reg1 x, b, c, d, e, h, l rp xa, bc, de, hl rp1 bc, de, hl rp2 bc, de rp xa, bc, de, hl, xa, bc, de, hl rp1 bc, de, hl, xa, bc, de, hl rpa hl, hl+, hlC, de, dl rpa1 de, dl n4 4-bit immediate data or label n8 8-bit immediate data or label mem 8-bit immediate data or label note bit 2-bit immediate data or label fmem fb0h to fbfh, ff0h to fffh immediate data or label pmem fc0h to fffh immediate data or label addr 0000h to 3fffh immediate data or label addr1 0000h to 3fffh immediate data or label (mk ii mode only) caddr 12-bit immediate data or label faddr 11-bit immediate data or label taddr 20h to 7fh immediate data (however, bit0 = 0) or label portn port0 to port3, port5, port6, port8, port9 iexxx iebt, iecsi, iet0 to iet2, ie0 to ie2, ie4, iew rbn rb0 to rb3 mbn mb0, mb1, mb15 note when processing 8-bit data, only even-numbered addresses can be specified. m pd75p3116 19 (2) operation legend a : a register; 4-bit accumulator b : b register c : c register d : d register e : e register h : h register l : l register x : x register xa : register pair (xa); 8-bit accumulator bc : register pair (bc) de : register pair (de) hl : register pair (hl) xa : expansion register pair (xa) bc : expansion register pair (bc) de : expansion register pair (de) hl : expansion register pair (hl) pc : program counter sp : stack pointer cy : carry flag; bit accumulator psw : program status word mbe : memory bank enable flag rbe : register bank enable flag portn : port n (n = 0 to 3, 5, 6, 8, 9) ime : interrupt master enable flag ips : interrupt priority selection register iexxx : interrupt enable flag rbs : register bank selection register mbs : memory bank selection register pcc : processor clock control register . : delimiter for address and bit (xx) : addressed data with xx xxh : hexadecimal data m pd75p3116 20 (3) description of symbols used in addressing area remarks 1. mb indicates access-enabled memory banks. 2. in area *2, mb = 0 for both mbe and mbs. 3. in areas *4 and *5, mb = 15 for both mbe and mbs. 4. areas *6 to *11 indicate corresponding address-enabled areas. (4) description of machine cycles s indicates the number of machine cycles required for skipping of skip-specified instructions. the value of s varies as shown below. ? no skip ..................................................................... s = 0 ? skipped instruction is 1-byte or 2-byte instruction .... s = 1 ? skipped instruction is 3-byte instruction note .............. s = 2 note 3-byte instructions: br !addr, bra !addr1, call !addr, and calla !addr1 caution the geti instruction is skipped for one machine cycle. one machine cycle equals one cycle (= t cy ) of the cpu clock f . use the pcc setting to select among four cycle times. mb = 0 (000h to 07fh) mb = 15 (f80h to fffh) mb = mbs mbs = 0, 1, 15 mb = mbe ?mbs mbs = 0, 1, 15 *1 mb = 0 *2 mbe = 1 : mbe = 0 : *3 mb = 15, fmem = fb0h to fbfh, ff0h to fffh mb = 15, pmem = fc0h to fffh addr = 0000h to 3fffh *4 *5 *6 addr, addr1 = *7 (current pc) ?5 to (current pc) ? (current pc) +2 to (current pc) +16 *8 caddr = 0000h to 0fffh (pc 13 , 12 = 00b) or 1000h to 1fffh (pc 13 , 12 = 01b) or 2000h to 2fffh (pc 13 , 12 = 10b) or 3000h to 3fffh (pc 13 , 12 = 11b) faddr = 0000h to 07ffh taddr = 0020h to 007fh addr1 = 0000h to 3fffh (mk ii mode only) *9 *10 *11 program memory addressing data memory addressing m pd75p3116 21 instruction mnemonic operand no. of machine operation addressing skip group bytes cycle area condition transfer mov a, #n4 1 1 a<-n4 string-effect a reg1, #n4 2 2 reg1<-n4 xa, #n8 2 2 xa<-n8 string-effect a hl, #n8 2 2 hl<-n8 string-effect b rp2, #n8 2 2 rp2<-n8 a, @hl 1 1 a<-(hl) *1 a, @hl+ 1 2+s a<-(hl), then l<-l+1 *1 l=0 a, @hlC 1 2+s a<-(hl), then l<-lC1 *1 l=fh a, @rpa1 1 1 a<-(rpa1) *2 xa, @hl 2 2 xa<-(hl) *1 @hl, a 1 1 (hl)<-a *1 @hl, xa 2 2 (hl)<-xa *1 a, mem 2 2 a<-(mem) *3 xa, mem 2 2 xa<-(mem) *3 mem, a 2 2 (mem)<-a *3 mem, xa 2 2 (mem)<-xa *3 a, reg 2 2 a<-reg xa, rp 2 2 xa<-rp reg1, a 2 2 reg1<-a rp1, xa 2 2 rp1<-xa xch a, @hl 1 1 a<->(hl) *1 a, @hl+ 1 2+s a<->(hl), then l<-l+1 *1 l=0 a, @hlC 1 2+s a<->(hl), then l<-lC1 *1 l=fh a, @rpa1 1 1 a<->(rpa1) *2 xa, @hl 2 2 xa<->(hl) *1 a, mem 2 2 a<->(mem) *3 xa, mem 2 2 xa<->(mem) *3 a, reg1 1 1 a<->reg1 xa, rp 2 2 xa<->rp table movt xa, @pcde 1 3 xa<-(pc 13-8 +de) rom reference xa, @pcxa 1 3 xa<-(pc 13-8 +xa) rom xa, @bcde note 1 3 xa<-(bcde) rom *6 xa, @bcxa note 1 3 xa<-(bcxa) rom *6 note only the lower 3 bits in the b register are valid. m pd75p3116 22 instruction mnemonic operand no. of machine operation addressing skip group bytes cycle area condition bit transfer mov1 cy, fmem.bit 2 2 cy<-(fmem.bit) *4 cy, pmem.@l 2 2 cy<-(pmem 7-2 +l 3-2 .bit(l 1-0 )) *5 cy, @h+mem.bit 2 2 cy<-(h+mem 3-0 .bit) *1 fmem.bit, cy 2 2 (fmem.bit)<-cy *4 pmem.@l, cy 2 2 (pmem 7-2 +l 3-2 .bit(l 1-0 ))<-cy *5 @h+mem.bit, cy 2 2 (h+mem 3-0 .bit)<-cy *1 arithmetic adds a, #n4 1 1+s a<-a+n4 carry xa, #n8 2 2+s xa<-xa+n8 carry a, @hl 1 1+s a<-a+(hl) *1 carry xa, rp 2 2+s xa<-xa+rp carry rp1, xa 2 2+s rp1<-rp1+xa carry addc a, @hl 1 1 a, cy<-a+(hl)+cy *1 xa, rp 2 2 xa, cy<-xa+rp+cy rp1, xa 2 2 rp1, cy<-rp1+xa+cy subs a, @hl 1 1+s a<-aC(hl) *1 borrow xa, rp 2 2+s xa<-xaCrp borrow rp1, xa 2 2+s rp1<-rp1Cxa borrow subc a, @hl 1 1 a, cy<-aC(hl)Ccy *1 xa, rp 2 2 xa, cy<-xaCrpCcy rp1, xa 2 2 rp1, cy<-rp1CxaCcy and a, #n4 2 2 a<-a ^ n4 a, @hl 1 1 a<-a ^ (hl) *1 xa, rp 2 2 xa<-xa ^ rp rp1, xa 2 2 rp1<-rp1 ^ xa or a, #n4 2 2 a<-a v n4 a, @hl 1 1 a<-a v (hl) *1 xa, rp 2 2 xa<-xa v rp rp1, xa 2 2 rp1<-rp1 v xa xor a, #n4 2 2 a<-a v n4 a, @hl 1 1 a<-a v (hl) *1 xa, rp 2 2 xa<-xa v rp rp1, xa 2 2 rp1<-rp1 v xa accumulator rorc a 1 1 cy<-a 0 , a 3 <-cy, a n-1 <-a n manipulation not a 2 2 a<-a increment/ incs reg 1 1+s reg<-reg+1 reg=0 decrement rp1 1 1+s rp1<-rp1+1 rp1=00h @hl 2 2+s (hl)<-(hl)+1 *1 (hl)=0 mem 2 2+s (mem)<-(mem)+1 *3 (mem)=0 decs reg 1 1+s reg<-regC1 reg=fh rp 2 2+s rp<-rpC1 rp=ffh m pd75p3116 23 instruction mnemonic operand no. of machine operation addressing skip group bytes cycle area condition comparison ske reg, #n4 2 2+s skip if reg=n4 reg=n4 @hl, #n4 2 2+s skip if (hl)=n4 *1 (hl)=n4 a, @hl 1 1+s skip if a=(hl) *1 a=(hl) xa, @hl 2 2+s skip if xa=(hl) *1 xa=(hl) a, reg 2 2+s skip if a=reg a=reg xa, rp 2 2+s skip if xa=rp xa=rp carry flag set1 cy 1 1 cy<-1 manipulation clr1 cy 1 1 cy<-0 skt cy 1 1+s skip if cy=1 cy=1 not1 cy 1 1 cy<-cy memory bit set1 mem.bit 2 2 (mem.bit)<-1 *3 manipulation fmem.bit 2 2 (fmem.bit)<-1 *4 pmem.@l 2 2 (pmem 7-2 +l 3-2 .bit(l 1-0 ))<-1 *5 @h+mem.bit 2 2 (h+mem 3-0 .bit)<-1 *1 clr1 mem.bit 2 2 (mem.bit)<-0 *3 fmem.bit 2 2 (fmem.bit)<-0 *4 pmem.@l 2 2 (pmem 7-2 +l 3-2 .bit(l 1-0 ))<-0 *5 @h+mem.bit 2 2 (h+mem 3-0 .bit)<-0 *1 skt mem.bit 2 2+s skip if(mem.bit)=1 *3 (mem.bit)=1 fmem.bit 2 2+s skip if(fmem.bit)=1 *4 (fmem.bit)=1 pmem.@l 2 2+s skip if(pmem 7-2 +l 3-2 .bit(l 1-0 ))=1 *5 (pmem.@l)=1 @h+mem.bit 2 2+s skip if(h+mem 3-0 .bit)=1 *1 (@h+mem.bit)=1 skf mem.bit 2 2+s skip if(mem.bit)=0 *3 (mem.bit)=0 fmem.bit 2 2+s skip if(fmem.bit)=0 *4 (fmem.bit)=0 pmem.@l 2 2+s skip if(pmem 7-2 +l 3-2 .bit(l 1-0 ))=0 *5 (pmem.@l)=0 @h+mem.bit 2 2+s skip if(h+mem 3-0 .bit)=0 *1 (@h+mem.bit)=0 sktclr fmem.bit 2 2+s skip if(fmem.bit)=1 and clear *4 (fmem.bit)=1 pmem.@l 2 2+s skip if(pmem 7-2 +l 3-2 .bit(l 1-0 ))=1 and clear *5 (pmem.@l)=1 @h+mem.bit 2 2+s skip if(h+mem 3-0 .bit)=1 and clear *1 (@h+mem.bit)=1 and1 cy, fmem.bit 2 2 cy<-cy ^ (fmem.bit) *4 cy, pmem.@l 2 2 cy<-cy ^ (pmem 7-2 +l 3-2 .bit(l 1-0 )) *5 cy, @h+mem.bit 2 2 cy<-cy ^ (h+mem 3-0 .bit) *1 or1 cy, fmem.bit 2 2 cy<-cy v (fmem.bit) *4 cy, pmem.@l 2 2 cy<-cy v (pmem 7-2 +l 3-2 .bit(l 1-0 )) *5 cy, @h+mem.bit 2 2 cy<-cy v (h+mem 3-0 .bit) *1 xor1 cy, fmem.bit 2 2 cy<-cy v (fmem.bit) *4 cy, pmem.@l 2 2 cy<- cy v (pmem 7-2 +l 3-2 .bit(l 1-0 )) *5 cy, @h+mem.bit 2 2 cy<-cy v (h+mem 3-0 .bit) *1 m pd75p3116 24 instruction mnemonic operand no. of machine operation addressing skip group bytes cycle area condition branch br note 1 addr pc 13-0 <-addr *6 use the assembler to select the most appropriate instruction among the following. ? br !addr ? brcb !caddr ? br $addr addr1 pc 13-0 <-addr1 *11 use the assembler to select the most appropriate instruction among the following. ? bra !addr1 ? br !addr ? brcb !caddr ? br $addr1 !addr 3 3 pc 13-0 <-addr *6 $addr 1 2 pc 13-0 <-addr *7 $addr1 1 2 pc 13-0 <-addr1 pcde 2 3 pc 13-0 <-pc 13-8 +de pcxa 2 3 pc 13-0 <-pc 13-8 +xa bcde 2 3 pc 13-0 <-bcde note 2 *6 bcxa 2 3 pc 13-0 <-bcxa note 2 *6 bra note 1 !addr1 3 3 pc 13-0 <-addr1 *11 brcb !caddr 2 2 pc 13-0 <-pc 13, 12 +caddr 11-0 *8 notes 1. the portion in a double box can be supported only in the mk ii mode. the others can be supported only in the mk i mode. 2. the b register is valid only for the lower two bits. m pd75p3116 25 instruction mnemonic operand no. of machine operation addressing skip group bytes cycle area condition subroutine calla note !addr1 3 3 (spC6)(spC3)(spC4)<-pc 11-0 *11 stack control (spC5)<-0, 0, pc 13 , 12 (spC2) <-x, x, mbe, rbe pc 13-0 <-addr1, sp<-spC6 call note !addr 3 3 (spC4)(spC1)(spC2)<-pc 11-0 *6 (spC3)<-mbe, rbe, pc 13, 12 pc 13-0 <-addr, sp<-spC4 4 (spC6)(spC3)(spC4) <- pc 11-0 (spC5)<-0, 0, pc 13, 12 (spC2)<-x, x, mbe, rbe pc 13-0 <-addr, sp<-spC6 callf note !faddr 2 2 (spC4)(spC1)(spC2)<-pc 11-0 *9 (spC3)<-mbe, rbe, pc 13, 12 pc 13-0 <-000+faddr, sp<-spC4 3 (spC6)(spC3)(spC4) <- pc 11-0 (spC5)<-0, 0, pc 13, 12 (spC2)<-x, x, mbe, rbe pc 13-0 <-000+faddr, sp<-spC6 ret note 1 3 mbe, rbe, pc 13, 12 <-(sp+1) pc 11-0 <-(sp)(sp+3)(sp+2) sp<-sp+4 x, x, mbe, rbe<-(sp+4) pc 11-0 <-(sp)(sp+3)(sp+2) 0, 0, pc 13, 12 <-(sp+1) sp<-sp+6 rets note 1 3+s mbe, rbe, pc 13, 12 <-(sp+1) unconditional pc 11-0 <-(sp)(sp+3)(sp+2) sp<-sp+4 then skip unconditionally x, x, mbe, rbe<-(sp+4) pc 11-0 <-(sp)(sp+3)(sp+2) 0, 0, pc 13, 12 <-(sp+1) sp<-sp+6 then skip unconditionally reti note 1 3 mbe, rbe, pc 13, 12 <-(sp+1) pc 11-0 <-(sp)(sp+3)(sp+2) psw<-(sp+4)(sp+5) sp<-sp+6 0, 0, pc 13, 12 <-(sp+1) pc 11-0 <-(sp)(sp+3)(sp+2) psw<-(sp+4)(sp+5), sp<-sp+6 note the portion in a double box can be supported only in the mk ii mode. other portions can be supported only in the mk i mode. m pd75p3116 26 instruction mnemonic operand no. of machine operation addressing skip group bytes cycle area condition subroutine push rp 1 1 (spC1)(spC2)<-rp, sp<-spC2 stack control bs 2 2 (spC1)<-mbs, (spC2)<-rbs, sp<-spC2 pop rp 1 1 rp<-(sp+1)(sp), sp<-sp+2 bs 2 2 mbs<-(sp+1), rbs<-(sp), sp<-sp+2 interrupt ei 2 2 ime(ips.3)<-1 control iexxx 2 2 iexxx<-1 di 2 2 ime(ips.3)<-0 iexxx 2 2 iexxx<-0 i/o in note 1 a, portn 2 2 a<-portn (n=0 to 3, 5, 6, 8, 9) xa, portn 2 2 xa<-portn+ 1 , portn (n=8) out note 1 portn, a 2 2 portn<-a (n=2 to 3, 5, 6, 8, 9) portn, xa 2 2 portn+ 1 , portn<-xa (n=8) cpu control halt 2 2 set halt mode(pcc.2<-1) stop 2 2 set stop mode(pcc.3<-1) nop 1 1 no operation special sel rbn 2 2 rbs<-n (n=0 to 3) mbn 2 2 mbs<-n (n=0, 1, 15) geti note 2, 3 taddr 1 3 ? when using tbr instruction *10 pc 13-0 <-(taddr) 5-0 +(taddr+1) ? when using tcall instruction (spC4)(spC1)(spC2)<-pc 11-0 (spC3)<-mbe, rbe, pc 13, 12 pc 13-0 <-(taddr) 5-0 +(taddr+1) sp<-spC4 ? when using instruction other than determined by tbr or tcall referenced execute (taddr)(taddr+1) instructions instruction 1 3 ? when using tbr instruction *10 pc 13-0 <-(taddr) 5-0 +(taddr+1) 4 ? when using tcall instruction (spC6)(spC3)(spC4)<-pc 11-0 (spC5)<-0, 0, pc 13, 12 (spC2)<-x, x, mbe, rbe pc 13-0 <-(taddr) 5-0 +(taddr+1) sp<-spC6 3 ? when using instruction other than determined by tbr or tcall referenced execute (taddr)(taddr+1) instructions instruction notes 1. setting mbe=0 or mbe=1, mbs=15 is required during the execution of in or out instruction. 2. tbr and tcall instructions are assembler pseudo-instructions for the geti instruction table definitions. 3. the portion in a double box can be supported only in the mk ii mode. other portions can be supported only in the mk i mode. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - m pd75p3116 27 8. one-time prom (program memory) write and verify the program memory contained in the m pd75p3116 is a 16384 x 8-bit one-time prom that can be electrically written one time only. the pins listed in the table below are used for this proms write/verify operations. clock input from the x1 pin is used instead of address input as a method for updating addresses. pin function v pp pin where program voltage is applied during program memory write/verify (usually v dd potential) x1, x2 clock input pins for address updating during program memory write/verify. input the x1 pins inverted signal to the x2 pin. md0 to md3 operation mode selection pin for program memory write/verify d0/p60 to d3/p63 8-bit data i/o pins for program memory write/verify (lower 4 bits) d4/p50 to d7/p53 (upper 4 bits) v dd pin where power supply voltage is applied. applies 1.8 to 5.5 v in normal operation mode and +6 v for program memory write/verify. caution pins not used for program memory write/verify should be connected to vss. 8.1 operation modes for program memory write/verify when +6 v is applied to the v dd pin and +12.5 v to the v pp pin, the m pd75p3116 enters the program memory write/verify mode. the following operation modes can be specified by setting pins md0 to md3 as shown below. operation mode specification operation mode v pp v dd md0 md1 md2 md3 +12.5 v +6 v h l h l zero-clear program memory address l h h h write mode l l h h verify mode h x h h program inhibit mode x: l or h m pd75p3116 28 8.2 program memory write procedure program memory can be written at high speed using the following procedure. (1) pull down unused pins to vss through resistors. set the x1 pin low. (2) supply 5 v to the v dd and v pp pins. (3) wait 10 m s. (4) select the program memory address zero-clear mode. (5) supply 6 v to v dd and 12.5 v to v pp pins. (6) write data in the 1-ms write mode. (7) select the verify mode. if the data is written, go to (8) and if not, repeat (6) and (7). (8) additional write. (x: number of write operations from (6) and (7)) x 1 ms (9) apply four pulses to the x1 pin to increment the program memory address by one. (10) repeat (6) to (9) until the end address is reached. (11) select the program memory address zero-clear mode. (12) return the v dd - and v pp -pin voltages to 5 v. (13) turn off the power. the following figure shows steps (2) to (9). v pp v dd v dd + 1 v dd v pp v dd x1 d0/p60 to d3/p63 d4/p50 to d7/p53 data input data output data input md0/p30 md1/p31 md2/p32 md3/p33 x repetitions write verify additional write address increment m pd75p3116 29 v pp v dd v dd + 1 v dd v pp v dd x1 data output data output md0/p30 md2/p32 md3/p33 md1/p31 ? d0/p60 to d3/p63 d4/p50 to d7/p53 8.3 program memory read procedure the m pd75p3116 can read program memory contents using the following procedure. (1) pull down unused pins to v ss through resistors. set the x1 pin low. (2) supply 5 v to the v dd and v pp pins. (3) wait 10 m s. (4) select the program memory address zero-clear mode. (5) supply 6 v to the v dd and 12.5 to the v pp pins. (6) select the verify mode. apply four pulses to the x1 pin. every four clock pulses will output the data stored in one address. (7) select the program memory address zero-clear mode. (8) return the v dd - and v pp -pin voltages to 5v. (9) turn off the power. the following figure shows steps (2) to (7). m pd75p3116 30 8.4 one-time prom screening due to its structure, the one-time prom cannot be fully tested before shipment by nec. therefore, nec recommends that after the required data is written and the prom is stored under the temperature and time conditions shown below, the prom should be verified via a screening. storage temperature storage time 125?c 24 hours nec offers qtop microcontrollers for which one-time prom writing, marking, screening, and verification are provided at additional cost. for more detailed information, contact an nec sales representative. 31 m pd75p3116 9. electrical specifications absolute maximum ratings (t a = 25?c) parameter symbol test conditions rating unit power supply voltage v dd C0.3 to +7.0 v prom power supply v pp C0.3 to +13.5 v voltage input voltage v i1 except port 5 C0.3 to v dd +0.3 v v i2 port 5 (n-ch open drain) C0.3 to +14 v output voltage v o C0.3 to v dd +0.3 v output current high i oh per pin C10 ma total of all pins C30 ma output current low i ol per pin 30 ma total of all pins 220 ma operating ambient t a C40 to +85 note ?c temperature storage temperature t stg C65 to +150 ?c note when lcd is driven in normal mode: t a = C10 to +85?c caution if any of the parameters exceeds the absolute maximum ratings, even momentarily, the reliability of the product may be impaired. the absolute maximum ratings are values that may physically damage the products. be sure to use the products within the ratings. capacitance (t a = 25?c, v dd = 0 v) parameter symbol test conditions min. typ. max. unit input capacitance c in f = 1 mhz 15 pf output capacitance c out unmeasured pins returned to 0 v. 15 pf i/o capacitance c io 15 pf 32 m pd75p3116 main system clock oscillator characteristics (t a = e40 to +85 c, v dd = 1.8 to 5.5 v) resonator recommended constant parameter test conditions min. typ. max. unit ceramic oscillation 1.0 6.0 note 2 mhz resonator frequency (fx) note 1 oscillation after v dd reaches oscil- 4 ms stabilization time note 3 lation voltage range min. crystal oscillation 1.0 6.0 note 2 mhz resonator frequency (fx) note 1 oscillation v dd = 4.5 to 5.5 v 10 ms stabilization time note 3 30 external x1 input 1.0 6.0 note 2 mhz clock frequency (fx) note 1 x1 input 83.3 500 ns high-/low-level width (t xh , t xl ) notes 1. the oscillation frequency and x1 input frequency indicate characteristics of the oscillator only. for the instruction execution time, refer to ac characteristics. 2. when the power supply voltage is 1.8 v v dd < 2.7 v and the oscillation frequency is 4.19 mhz < fx 6.0 mhz, setting the processor clock control register (pcc) to 0011 results in 1 machine cycle being less than the required 0.95 m s. therefore, set pcc to a value other than 0011. 3. the oscillation stabilization time is necessary for oscillation to stabilize after applying v dd or releasing the stop mode. caution when using the main system clock oscillator, wiring in the area enclosed with the dotted line should be carried out as follows to avoid an adverse effect from wiring capacitance. ? wiring should be as short as possible. ? wiring should not cross other signal lines. ? wiring should not be placed close to a varying high current. ? the potential of the oscillator capacitor ground should be the same as v dd . ? do not ground to a ground pattern in which a high current flows. ? do not fetch a signal from the oscillator. x2 x1 c1 c2 v dd x2 x1 c1 c2 v dd x1 x2 33 m pd75p3116 subsystem clock oscillator characteristics (t a = e40 to +85?c, v dd = 1.8 to 5.5 v) resonator recommended constant parameter test conditions min. typ. max. unit crystal oscillation 32 32.768 35 khz resonator frequency (f xt ) note 1 oscillation v dd = 4.5 to 5.5 v 1.0 2 s stabilization time note 2 10 external xt1 input frequency 32 100 khz clock (f xt ) note 1 xt1 input high-/low-level 515 m s width (t xth , t xtl ) notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. the oscillation stabilization time is necessary for oscillation to stabilize after applying v dd . caution when using the subsystem clock oscillator, wiring in the area enclosed with the dotted line should be carried out as follows to avoid an adverse effect from wiring capacitance. ? wiring should be as short as possible. ? wiring should not cross other signal lines. ? wiring should not be placed close to a varying high current. ? the potential of the oscillator capacitor ground should be the same as v dd . ? do not ground to a ground pattern in which a high current flows. ? do not fetch a signal from the oscillator. the subsystem clock oscillator is designed as a low amplification circuit to provide low consumption current, and is more liable to misoperation by noise than the main system clock oscillation circuit. special care should therefore be taken regarding the wiring method when the subsystem clock is used. xt2 xt1 c4 v dd c3 r xt1 xt2 34 m pd75p3116 dc characteristics (t a = e40 to +85?c, v dd = 1.8 to 5.5 v) parameter symbol test conditions min. typ. max. unit output current low i ol per pin 15 ma total of all pins 150 ma input voltage high v ih1 ports 2, 3, 8, and 9 2.7 v dd 5.5 v 0.7v dd v dd v 1.8 v dd < 2.7 v 0.9v dd v dd v v ih2 ports 0, 1, 6, reset 2.7 v dd 5.5 v 0.8v dd v dd v 1.8 v dd < 2.7 v 0.9v dd v dd v v ih3 port 5 2.7 v dd 5.5 v 0.7v dd 13 v (n-ch open-drain) 1.8 v dd < 2.7 v 0.9v dd 13 v v ih4 x1, xt1 v dd C 0.1 v dd v input voltage low v il1 ports 2, 3, 5, 8, and 9 2.7 v dd 5.5 v 0 0.3v dd v 1.8 v dd < 2.7 v 0 0.1v dd v v il2 ports 0, 1, 6, reset 2.7 v dd 5.5 v 0 0.2v dd v 1.8 v dd < 2.7 v 0 0.1v dd v v il3 x1, xt1 0 0.1 v output voltage high v oh sck, so, ports 2, 3, 6, 8, and 9 i oh = C1.0 ma v dd C 0.5 v output voltage low v ol1 sck, so, ports 2, 3, 5, 6, 8, and 9 i ol = 15 ma, 0.2 2.0 v v dd = 4.5 to 5.5 v i ol = 1.6 ma 0.4 v v ol2 sb0, sb1 when n-ch open-drain 0.2v dd v pull-up resistor 3 1 k w input leakage i lih1 v in = v dd pins other than x1, xt1 3 m a current high i lih2 x1, xt1 20 m a i lih3 v in = 13 v port 5 (n-ch open-drain) 20 m a input leakage i lil1 v in = 0 v pins other than x1, xt1, and port 5 C3 m a current low i lil2 x1, xt1 C20 m a i lil3 port 5 (n-ch open-drain) C3 m a when another instruction than input instruction is executed port 5 (n-ch open-drain) C30 m a when input instruction v dd = 5.0 v C10 C27 m a is executed v dd = 3.0 v C3 C8 m a output leakage i loh1 v out = v dd sck, so/sb0, sb1, ports 2, 3, 6, 8, and 9 3 m a current high i loh2 v out = 13 v port 5 (n-ch open-drain) 20 m a output leakage i lol v out = 0 v C3 m a current low on-chip pull-up resistor r l v in = 0 v ports 0, 1, 2, 3, 6, 8, and 9 50 100 200 k w (excluding p00 pin) 35 m pd75p3116 low power consump- tion mode note 9 dc characteristics (t a = C40 to +85?c, v dd = 1.8 to 5.5 v) parameter symbol test conditions min. typ. max. unit lcd drive voltage v lcd vac0 = 0 t a = C40 to +85 c 2.7 v dd v t a = C10 to +85 c 2.2 v dd v vac0 = 1 1.8 v dd v vac current note 1 i vac vac0 = 1, v dd = 2.0 v 10% 1 4 m a lcd output voltage v odc lo = 1.0 m av lcd0 = v lcd 0 0.2 v deviation note 2 (common) v lcd1 = v lcd x 2/3 lcd output voltage v ods lo = 0.5 m av lcd2 = v lcd x 1/3 0 0.2 v deviation note 2 (segment) 1.8 v v lcd v dd supply current note 3 i dd1 6.00 mhz note 4 v dd = 5.0 v 10% note 5 3.2 9.5 ma crystal oscillation v dd = 3.0 v 10% note 6 0.55 1.6 ma i dd2 c1 = c2 = 22 pf halt mode v dd = 5.0 v 10% 0.7 2.0 ma v dd = 3.0 v 10% 0.25 0.8 ma i dd1 4.19 mhz note 4 v dd = 5.0 v 10% note 5 2.5 7.5 ma crystal oscillation v dd = 3.0 v 10% note 6 0.45 1.35 ma i dd2 c1 = c2 = 22 pf halt mode v dd = 5.0 v 10% 0.65 1.8 ma v dd = 3.0 v 10% 0.22 0.7 ma i dd3 32.768 khz note 7 low-voltage v dd = 3.0 v 10% 45 130 m a crystal oscillation mode note 8 v dd = 2.0 v 10% 20 55 m a v dd = 3.0 v, t a = 25?c 45 90 m a v dd = 3.0 v 10% 42 120 m a v dd = 3.0 v, t a = 25?c 42 85 m a i dd4 halt mode v dd = 3.0 v 10% 5.5 18 m a v dd = 2.0 v 10% 2.2 7 m a v dd = 3.0 v, t a = 25?c 5.5 12 m a v dd = 3.0 v 10% 4.0 12 m a v dd = 3.0 v, 4.0 8 m a t a = 25?c i dd5 xt1 = 0 v note 10 v dd = 5.0 v 10% 0.05 10 m a stop mode v dd = 3.0 v 0.02 5 m a 10% t a = 25?c 0.02 3 m a notes 1. set to vac0 = 0 when the low power consumption mode and the stop mode are used. if vac0 = 1 is set, the current increases for approx. 1 m a. 2. the voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and common outputs (v lcdn ; n = 0, 1, 2). 3. not including currents flowing in on-chip pull-up resistors. 4. including oscillation of the subsystem clock. 5. when the processor clock control register (pcc) is set to 0011 and the device is operated in the high- speed mode. 6. when pcc is set to 0000 and the device is operated in the low-speed mode. 7. when the system clock control register (scc) is set to 1001 and the device is operated on the subsystem clock, with main system clock oscillation stopped. 8. when the sub-oscillation circuit control register (sos) is set to 0000. 9. when sos is set to 0010. 10. when sos is set to 00 1 and the feedback resistor of the sub-oscillation circuit is not used. low power consumption mode note 9 low- voltage mode note 8 36 m pd75p3116 ac characteristics (t a = e40 to +85?c, v dd = 1.8 to 5.5 v) parameter symbol test conditions min. typ. max. unit cpu clock cycle t cy operating on v dd = 2.7 to 5.5 v 0.67 64 m s time note 1 main system clock 0.95 64 m s (min. instruction execution operating on subsystem clock 114 122 125 m s time = 1 machine cycle) ti0, ti1, ti2 input f ti v dd = 2.7 to 5.5 v 0 1.0 mhz frequency 0 275 khz ti0, ti1, ti2 input t tih , t til v dd = 2.7 to 5.5 v 0.48 m s high-/low-level width 1.8 m s interrupt input high-/ t inth , t intl int0 im02 = 0 note 2 m s low-level width im02 = 1 10 m s int1, 2, 4 10 m s kr0 to kr7 10 m s reset low-level width t rsl 10 m s notes 1. the cycle time (minimum instruction execution time) of the cpu clock ( f ) is determined by the oscillation frequency of the connected resonator (and external clock), the system clock control register (scc) and the processor clock control register (pcc). the figure at the right indicates the cycle time t cy versus supply voltage v dd characteristic with the main system clock operating. 2. 2t cy or 128/fx is set by setting the interrupt mode register (im0). 1 0 23456 0.5 1 3 2 4 5 6 60 64 supply voltage v dd [v] t cy vs v dd (at main system clock operation) cycle time t cy [ s] guaranteed operation range 37 m pd75p3116 serial transfer operation 2-wire and 3-wire serial i/o mode (sck...internal clock output): (t a = e40 to +85?c, v dd = 1.8 to 5.5 v) parameter symbol test conditions min. typ. max. unit sck cycle time t kcy1 v dd = 2.7 to 5.5 v 1300 ns 3800 ns sck high-/low-level t kl1 , t kh1 v dd = 2.7 to 5.5 v t kcy1 /2C50 ns width t kcy1 /2C150 ns si note 1 setup time t sik1 v dd = 2.7 to 5.5 v 150 ns (to sck - ) 500 ns si note 1 hold time t ksi1 v dd = 2.7 to 5.5 v 400 ns (from sck - ) 600 ns sck ? so note 1 output t kso1 r l = 1 k w ,v dd = 2.7 to 5.5 v 0 250 ns delay time c l = 100 pf note 2 0 1000 ns notes 1. in 2-wire serial i/o mode, read this parameter as sb0 or sb1 instead. 2. r l and c l are the load resistance and load capacitance of the so output lines, respectively. 2-wire and 3-wire serial i/o mode (sck...external clock input): (t a = C40 to +85?c, v dd = 1.8 to 5.5 v) parameter symbol test conditions min. typ. max. unit sck cycle time t kcy2 v dd = 2.7 to 5.5 v 800 ns 3200 ns sck high-/low-level t kl2 , t kh2 v dd = 2.7 to 5.5 v 400 ns width 1600 ns si note 1 setup time t sik2 v dd = 2.7 to 5.5 v 100 ns (to sck - ) 150 ns si note 1 hold time t ksi2 v dd = 2.7 to 5.5 v 400 ns (from sck - ) 600 ns sck ? so note 1 output t kso2 r l = 1 k w ,v dd = 2.7 to 5.5 v 0 300 ns delay time c l = 100 pf note 2 0 1000 ns notes 1. in 2-wire serial i/o mode, read this parameter as sb0 or sb1 instead. 2. r l and c l are the load resistance and load capacitance of the so output lines, respectively. 38 m pd75p3116 sbi mode (sck...internal clock output (master)): (t a = e40 to +85?c, v dd = 1.8 to 5.5 v) parameter symbol test conditions min. typ. max. unit sck cycle time t kcy3 v dd = 2.7 to 5.5 v 1300 ns 3800 ns sck high-/low-level t kl3 , t kh3 v dd = 2.7 to 5.5 v t kcy3 /2C50 ns width t kcy3 /2C150 ns sb0, 1 setup time t sik3 v dd = 2.7 to 5.5 v 150 ns (to sck - ) 500 ns sb0, 1 hold time (from sck - ) t ksi3 t kcy3 /2 ns sck ? sb0, 1 t kso3 r l = 1 k w ,v dd = 2.7 to 5.5 v 0 250 ns output delay time c l = 100 pf note 0 1000 ns sck -? sb0, 1 t ksb t kcy3 ns sb0, 1 ? sck t sbk t kcy3 ns sb0, 1 low-level width t sbl t kcy3 ns sb0, 1 high-level width t sbh t kcy3 ns note r l and c l are the load resistance and load capacitance of the sb0 and sb1 output lines, respectively. sbi mode (sck...external clock input (slave)): (t a = C40 to +85?c, v dd = 1.8 to 5.5 v) parameter symbol test conditions min. typ. max. unit sck cycle time t kcy4 v dd = 2.7 to 5.5 v 800 ns 3200 ns sck high-/low-level t kl4 , t kh4 v dd = 2.7 to 5.5 v 400 ns width 1600 ns sb0, 1 setup time t sik4 v dd = 2.7 to 5.5 v 100 ns (to sck - ) 150 ns sb0, 1 hold time (from sck - ) t ksi4 t kcy4 /2 ns sck ? sb0, 1 output t kso4 r l = 1 k w ,v dd = 2.7 to 5.5 v 0 300 ns delay time c l = 100 pf note 0 1000 ns sck -? sb0, 1 t ksb t kcy4 ns sb0, 1 ? sck t sbk t kcy4 ns sb0, 1 low-level width t sbl t kcy4 ns sb0, 1 high-level width t sbh t kcy4 ns note r l and c l are the load resistance and load capacitance of the sb0 and sb1 output lines, respectively. 39 m pd75p3116 ac timing test point (excluding x1, xt1 input) clock timing ti0, ti1, ti2 timing ti0, ti1, ti2 1/f ti t til t tih x1 input 1/f x t xl t xh 0.1 v v dd ?.1 v xt1 input 1/f xt t xtl t xth 0.1 v v dd ?.1 v v ih (min.) v il (max.) v ih (min.) v il (max.) v oh (min.) v ol (max.) v oh (min.) v ol (max.) 40 m pd75p3116 serial transfer timing 3-wire serial i/o mode 2-wire serial i/o mode t kcy1, 2 t kl1, 2 t kh1, 2 sck si so t sik1, 2 t ksi1, 2 t kso1, 2 input data output data t kso1, 2 t sik1, 2 t kl1, 2 t kh1, 2 sck t ksi1, 2 sb0, 1 t kcy1, 2 41 m pd75p3116 t kcy3, 4 t kh3, 4 t ksi3, 4 t sik3, 4 t kso3, 4 sck sb0, 1 t kl3, 4 t sbk t ksb t kcy3, 4 t kh3, 4 t ksi3, 4 t sik3, 4 t kso3, 4 sck sb0, 1 t kl3, 4 t sbk t sbh t sbl t ksb serial transfer timing bus release signal transfer command signal transfer interrupt input timing reset input timing t rsl reset t intl t inth int0, 1, 2, 4 kr0 to 7 42 m pd75p3116 data memory stop mode low supply voltage data retention characteristics (t a = e40 to +85?c) parameter symbol test conditions min. typ. max. unit release signal set time t srel 0 m s oscillation stabilization t wait release by reset 2 15 /f x ms wait time note 1 release by interrupt request note 2 ms notes 1. the oscillation stabilization wait time is the time during which the cpu operation is stopped to prevent unstable operation at the oscillation start. 2. depends on the basic interval timer mode register (btm) settings (see the table below). btm3 btm2 btm1 btm0 wait time fx = at 4.19 mhz fx = at 6.0 mhz 0002 20 /fx (approx. 250 ms) 2 20 /fx (approx. 175 ms) 0112 17 /fx (approx. 31.3 ms) 2 17 /fx (approx. 21.8 ms) 1012 15 /fx (approx. 7.81 ms) 2 15 /fx (approx. 5.46 ms) 1112 13 /fx (approx. 1.95 ms) 2 13 /fx (approx. 1.37 ms) 43 m pd75p3116 data retention timing (stop mode release by reset) data retention timing (standby release signal: stop mode release by interrupt signal) v dd reset stop instruction execution stop mode data retention mode internal reset operation halt mode operating mode t srel t wait t srel t wait v dd stop instruction execution stop mode data retention mode halt mode operating mode standby release signal (interrupt request) 44 m pd75p3116 dc programming characteristics (t a = 25 5?c, v dd = 6.0 0.25 v, v pp = 12.5 0.3 v, v ss = 0 v) parameter symbol test conditions min. typ. max. unit input voltage high v ih1 except x1 and x2 pins 0.7v dd v dd v v ih2 x1, x2 v dd C0.5 v dd v input voltage low v il1 except x1 and x2 pins 0 0.3v dd v v il2 x1, x2 0 0.4 v input leakage current i li v in = v il or v ih 10 m a output voltage high v oh i oh = C1 ma v dd C1.0 v output voltage low v ol i ol = 1.6 ma 0.4 v v dd power supply current i dd 30 ma v pp power supply current i pp md0 = v il , md1 = v ih 30 ma cautions 1. avoid exceeding +13.5 v for v pp including the overshoot. 2. v dd must be applied before v pp , and cut after v pp . ac programming characteristics (t a = 25 5?c, v dd = 6.0 0.25 v, v pp = 12.5 0.3 v, v ss = 0 v) parameter symbol note 1 test conditions min. typ. max. unit address setup time note 2 (to md0 )t as t as 2 m s md1 setup time (to md0 )t m1s t oes 2 m s data setup time (to md0 )t ds t ds 2 m s address hold time note 2 (from md0 - )t ah t ah 2 m s data hold time (from md0 - )t dh t dh 2 m s md0 -? data output float delay time t df t df 0 130 ns v pp setup time (to md3 - )t vps t vps 2 m s v dd setup time (to md3 - )t vds t vcs 2 m s initial program pulse width t pw t pw 0.95 1.0 1.05 ms additional program pulse width t opw t opw 0.95 21.0 ms md0 setup time (to md1 - )t m0s t ces 2 m s md0 ? data output delay time t dv t dv md0 = md1 = v il 1 m s md1 hold time (from md0 - )t m1h t oeh t m1h +t m1r 3 50 m s2 m s md1 recovery time (from md0 )t m1r t or 2 m s program counter reset time t pcr C10 m s x1 input high-/low-level width t xh , t xl C 0.125 m s x1 input frequency f x C 4.19 mhz initial mode set time t i C2 m s md3 setup time (to md1 - )t m3s C2 m s md3 hold time (from md1 )t m3h C2 m s md3 setup time (to md0 )t m3sr C during program memory read 2 m s address note 2 ? data output delay time t dad t acc during program memory read 2 m s address note 2 ? data output hold time t had t oh during program memory read 0 130 ns md3 hold time (from md0 - )t m3hr C during program memory read 2 m s md3 ? data output float delay time t dfr C during program memory read 2 m s notes1. corresponding symbol of m pd27c256a 2. the internal address signal is incremented by 1 at the rising edge of the fourth x1 input and is not connected to a pin. 45 m pd75p3116 program memory write timing program memory read timing t vps t vds t xh t xl t i t ds t dh t dv t df t ds t dh t ah t as t pw t m1r t m0s t opw t m1s t m1h t pcr t m3s t m3h data input data output data input data input v pp v dd v dd +1 v dd v pp v dd x1 d0/p60 to d3/p60 d4/p50 to d7/p53 md0/p30 md1/p31 md2/p32 md3/p33 t vps t vds v pp v dd v dd +1 v dd v pp v dd t xh t xl t had t dad t dv t i t m3hr t dfr t pcr t m3sr x1 d0/p60 to d3/p60 d4/p50 to d7/p53 md0/p30 md1/p31 md2/p32 md3/p33 data output data output 46 m pd75p3116 10. characteristic curves (reference values) 10 5.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 012345678 (t a = 25 c) supply voltage v dd (v) supply current i dd (ma) pcc = 0010 pcc = 0001 pcc = 0000 main system clock halt mode + 32-khz oscillation xt1 xt2 x1 x2 crystal resonator 6.0 mhz crystal resonator 32.768 khz 330 k w 22 pf 22 pf 22 pf 22 pf v dd v dd main system clock stop mode + 32-khz oscillation (sos.1 = 1) and subsystem clock halt mode (sos.1 = 1) i dd vs v dd (main system clock: 6.0-mhz crystal resonator) pcc = 0011 main system clock stop mode + 32-khz oscillation (sos.1 = 0) and subsystem clock halt mode (sos.1 = 0) subsystem clock operation mode (sos.1 = 0) 47 m pd75p3116 10 5.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 012345678 xt1 xt2 x1 x2 crystal resonator 4.19 mhz crystal resonator 32.768 khz 330 k w 22 pf 22 pf 22 pf 22 pf supply voltage v dd (v) supply current i dd (ma) v dd v dd pcc = 0010 main system clock halt mode + 32-khz oscillation subsystem clock halt mode (sos.1 = 0) and main system clock stop mode + 32-khz oscillation (sos.1 = 0) subsystem clock operation mode (sos.1 = 0) i dd vs v dd (main system clock: 4.19-mhz crystal resonator) (t a = 25 c) main system clock stop mode + 32-khz oscillation (sos.1 = 1) and subsystem clock halt mode (sos.1 = 1) pcc = 0001 pcc = 0000 pcc = 0011 48 m pd75p3116 11. package drawings n a m f b 48 49 32 k l 64 pin plastic qfp ( 14) 64 1 17 16 33 d c detail of lead end s q 55 p m i h j g p64gc-80-ab8-3 item millimeters inches a b c d f g h i j k l 17.6 0.4 14.0 0.2 1.0 0.35 0.10 0.15 14.0 0.2 0.693 0.016 0.039 0.039 0.006 0.031 (t.p.) 0.551 note m n 0.10 0.15 1.8 0.2 0.8 (t.p.) 0.004 0.006 +0.004 ?.003 each lead centerline is located within 0.15 mm (0.006 inch) of its true position (t.p.) at maximum material condition. 0.071 0.008 0.014 0.551 0.8 0.2 0.031 p 2.55 0.100 0.693 0.016 17.6 0.4 1.0 +0.009 ?.008 q 0.1 0.1 0.004 0.004 s 2.85 max. 0.112 max. +0.10 ?.05 +0.009 ?.008 +0.004 ?.005 +0.009 ?.008 49 m pd75p3116 64 pin plastic lqfp ( 12) item millimeters inches d f g k i j 1.125 1.125 1.4?.2 0.65 (t.p.) 0.13 14.8?.4 q 0.583?.016 0.044 0.044 0.055?.008 0.005 0.026 (t.p.) p64gk-65-8a8-1 a f note each lead centerline is located within 0.13 mm (0.005 inch) of its true position (t.p.) at maximum material condition. c 12.0?.2 0.472 m 0.15 0.006 0.125?.075 0.005?.003 +0.004 ?.003 +0.009 ?.008 a 14.8?.4 0.583?.016 h 0.30?.10 0.012 +0.004 ?.005 l 0.6?.2 0.024 +0.008 ?.009 n 0.10 0.004 p 1.4 0.055 s r 1.7 max. 5 ? 0.067 max. 5 ? +0.10 ?.05 b 12.0?.2 0.472 +0.009 ?.008 m 48 49 32 64 1 17 16 33 b g h i j c d p n l k m detail of lead end s q r 50 m pd75p3116 12. recommended soldering conditions the m pd75p3116 should be soldered and mounted under the conditions recommended in the table below. for details of recommended soldering conditions, refer to the information document semiconductor device mounting technology manual (c10535e). for soldering methods and conditions other than those recommended below, contact an nec sales representative. table 12-1. surface mounting type soldering conditions (1) m pd75p3116gc-ab8: 64-pin plastic qfp (14 x 14 mm, 0.8-mm pitch) soldering soldering conditions symbol method infrared package peak temperature: 235 c, time: 30 seconds max. (at 210 c min.), ir35-00-3 reflow number of times: three times max. vps package peak temperature: 215 c, time: 40 seconds max. (at 200 c min.), vp15-00-3 number of times: three times max. wave soldering solder temperature: 260 c max., flow time: 10 seconds max., number of ws60-00-1 times: once, preheating temperature: 120 c max. (package surface temperature) partial heating pin temperature: 300 c max., time : 3 seconds max. (per device) caution use of more than one soldering method should be avoided (except for partial heating). (2) m pd75p3116gk-8a8: 64-pin plastic qfp (12 x 12 mm, 0.65-mm pitch) soldering recommended method soldering conditions conditions reference code infrared reflow package peak temperature: 235 c, ir35-107-2 time: 30 seconds max. (at 210?c min.), number of times: twice max., number of days: 7 note (after that, prebaking is necessary at 125 c for 10 hours) 51 m pd75p3116 appendix a. function list of m pd75308b, 753108 and 75p3116 parameter m pd75308b m pd753108 m pd75p3116 program memory mask rom mask rom one-time prom 0000h to 1f7fh 0000h to 1fffh 0000h to 3fffh (8064 x 8 bits) (8192 x 8 bits) (16384 x 8 bits) data memory 000h to 1ffh (512 x 4 bits) cpu 75x standard 75xl cpu instruction when main system 0.95, 1.91, 15.3 m s ? 0.95, 1.91, 3.81, 15.3 m s (during 4.19-mhz operation) execution clock is selected (during 4.19-mhz operation) ? 0.67, 1.33, 2.67, 10.7 m s (during 6.0-mhz operation) time when subsystem 122 m s (during 32.768-khz operation) clock is selected stack sbs register none sbs.3 = 1: mk i mode selection sbs.3 = 0: mk ii mode selection stack area 000h to 0ffh 000h to 1ffh subroutine call instruc- 2-byte stack when mk i mode : 2-byte stack tion stack operation when mk ii mode : 3-byte stack instruction bra !addr1 unavailable when mk i mode : unavailable calla !addr1 when mk ii mode : available movt xa, @bcde available movt xa, @bcxa br bcde br bcxa call !addr 3 machine cycles mk i mode : 3 machine cycles mk ii mode : 4 machine cycles callf !faddr 2 machine cycles mk i mode : 2 machine cycles mk ii mode : 3 machine cycles i/o port cmos input 8 8 cmos input/output 16 20 bit port output 8 0 n-ch open-drain 8 4 input/output total 40 32 lcd controller/driver segment selection: 24/28/32 segment selection: 16/20/24 segments (can be changed to cmos (can be changed to cmos input/output port in input/output port in 4-unit; 4-unit; max. 8) max. 8) display mode selection: static, 1/2 duty (1/2 bias), 1/3 duty (1/2 bias), 1/3 duty (1/3 bias), 1/4 duty (1/3 bias) on-chip split resistor for lcd driver can be specified by no on-chip split resistor using mask option. for lcd driver timer 3 channels 5 channels ? basic interval timer: ? basic interval timer/watchdog timer: 1 channel 1 channel ? 8-bit timer/event counter: 3 channels ? 8-bit timer/event counter: (can be used as 16-bit timer/event counter) 1 channel ? watch timer: 1 channel ? watch timer: 1 channel 52 m pd75p3116 parameter m pd75308b m pd753108 m pd75p3116 clock output (pcl) ? f , 524, 262, 65.5 khz ? f , 524, 262, 65.5 khz (main system clock: (main system clock: during 4.19-mhz operation) during 4.19-mhz ? f , 750, 375, 93.8 khz operation) (main system clock: during 6.0-mhz operation) buz output (buz) 2 khz ? 2, 4, 32 khz (main system clock: (main system clock: during 4.19-mhz operation or during 4.19-mhz operation) subsystem clock: during 32.768-khz operation) ? 2.93, 5.86, 46.9 khz (main system clock: 6.0-mhz operation) serial interface 3 modes are available ? 3-wire serial i/o mode msb/lsb can be selected for transfer first bit ? 2-wire serial i/o mode ? sbi mode sos register feedback resistor none contained cut flag (sos.0) sub-oscillation circuit none contained current cut flag (sos.1) register bank selection register (rbs) none yes standby release by int0 no yes vectored interrupt external: 3, internal: 3 external: 3, internal: 5 supply voltage v dd = 2.0 to 6.0 v v dd = 1.8 to 5.5 v operating ambient temperature t a = C40 to +85 c package ? 80-pin plastic qfp ? 84-pin plastic qfp (14 x 14 mm, 0.8-mm pitch) (14 x 20 mm) ? 64-pin plastic qfp (12 x 12 mm, 0.65-mm pitch) ? 80-pin plastic qfp (14 x 14 mm) ? 80-pin plastic tqfp (fine pitch) (12 x 12 mm) 53 m pd75p3116 appendix b. development tools the following development tools have been provided for system development using the m pd75p3116. in the 75xl series, a common relocatable assembler is used in combination with a device file dedicated to each model. ra75x relocatable assembler host machine part no. (name) os supply medium pc-9800 series ms-dos tm 3.5" 2hd m s5a13ra75x ver.3.30 to 5" 2hd m s5a10ra75x ver.6.2 note ibm pc/at tm refer to os for 3.5" 2hc m s7b13ra75x or compatibles ibm pcs 5" 2hc m s7b10ra75x device file host machine part no. (name) os supply medium pc-9800 series ms-dos 3.5" 2hd m s5a13df753108 ver.3.30 to 5" 2hd m s5a10df753108 ver.6.2 note ibm pc/at refer to os for 3.5" 2hc m s7b13df753108 or compatibles ibm pcs 5" 2hc m s7b10df753108 note ver. 5.00 and later include a task swapping function, but this function cannot be used in this software. remark operation of the assembler and device file is guaranteed only when using the host machine and os described above. 54 m pd75p3116 prom write tools hardware pg-1500 this is a prom writer that can program single-chip microcontroller with prom in stand-alone mode or under control of host machine when connected with supplied accessory board and optional programmer adapter. it can also program typical proms in capacities ranging from 256 k to 4 m bits. pa-75p3116bgc this is a prom programmer adapter for the m pd75p3116gc. it can be used when connected to a pg-1500. pa-75p3116bgk this is a prom programmer adapter for the m pd75p3116gk. it can be used when connected to a pg-1500. software pg-1500 controller connects pg-1500 to host machine with serial and parallel interface and controls pg-1500 on host machine. host machine part no. (name) os supply medium pc-9800 series ms-dos 3.5" 2hd m s5a13pg1500 ver.3.30 to 5" 2hd m s5a10pg1500 ver.6.2 note ibm pc/at refer to os for 3.5" 2hd m s7b13pg1500 or compatible ibm pcs 5" 2hc m s7b10pg1500 note ver. 5.00 and later include a task swapping function, but this function cannot be used in this software. remark operation of the pg-1500 controller is guaranteed only when using the host machine and os described above. 55 m pd75p3116 debugging tools in-circuit emulators (ie-75000-r and ie-75001-r) are provided as program debugging tools for the m pd75p3116. various system configurations using these in-circuit emulators are listed below. hardware ie-75000-r note 1 the ie-75000-r is an in-circuit emulator to be used for hardware and software debugging during development of application systems using the 75x or 75xl series products. for development of the m pd753108 subseries, the ie-75000-r is used with optional emulation board (ie-75300-r-em) and emulation probe (ep-753108gc-r or ep-753108gk-r). highly efficient debugging can be performed when connected to host machine and prom programmer. the ie-75000-r includes a connected emulation board (ie-75000-r-em). ie-75001-r the ie-75001-r is an in-circuit emulator to be used for hardware and software debugging during development of application systems using the 75x or 75xl series products. the ie-75001-r is used in combination with optional emulation board (ie-75300-r-em) and emulation probe (ep-753108gc-r or ep-753108gk-r). highly efficient debugging can be performed when connected to host machine and prom programmer. ie-75300-r-em this is an emulation board for evaluating application systems using the m pd75p3116. it is used in combination with the ie-75000-r or ie-75001-r. ep-753108gc-r this is an emulation probe for the m pd75p3116gc. when being used, it is connected with the ie-75000-r or ie-75001-r and the ie-75300-r-em. ev-9200gc-64 it includes a 64-pin conversion socket (ev-9200gc-64) to facilitate connections with target system. ep-753108gk-r this is an emulation probe for the m pd75p3116gk. when being used, it is connected with the ie-75000-r or ie-75001-r and the ie-75300-r-em. tgk-064sbw it includes a 64-pin conversion adapter (tgk-064sbw) to facilitate connections with target system. software ie control program this program can control the ie-75000-r or ie-75001-r on a host machine when connected to the ie-75000-r or ie-75001-r via an rs-232c or centronics interface. host machine part no. (name) os supply medium pc-9800 series ms-dos 3.5" 2hd m s5a13ie75x ver.3.30 to 5" 2hd m s5a10ie75x ver.6.2 note 3 ibm pc/at refer to os for 3.5" 2hc m s7b13ie75x or compatible ibm pcs 5" 2hc m s7b10ie75x notes 1. this is a maintenance product. 2. made by tokyo eletech corporation (tokyo, 03-5295-1661). contact to an nec sales representative for detailed information. 3. ver. 5.00 and later include a task swapping function, but this function cannot be used in this software. remarks 1. operation of the ie control program is guaranteed only when using the host machine and os described above. 2. the m pd753104, 753106, 753108, and 75p3116 are generically called the m pd753108 subseries. note 2 56 m pd75p3116 os for ibm pcs the following operating systems for the ibm pc are supported. os version pc dos tm ver.3.1 to 6.3, j6.1/v note to j6.3/v note ms-dos ver.5.0 to 6.2 5.0/v note to 6.2/v note ibm dos tm j5.02/v note note only english mode is supported. caution ver. 5.0 and later include a task swapping function, but this function cannot be used in this software. 57 m pd75p3116 appendix c. related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. device related documents document name document no. english japanese m pd753104, 753106, and 753108 data sheet u10086e u10086j m pd75p3116 data sheet u11369e (this document) u11369j m pd753108 users manual u10890e u10890j m pd753108 instruction table C iem-5600 75xl series selection guide u10453e u10453j development tool related documents document name document no. english japanese hardware ie-75000-r/ie-75001-r users manual eeu-1416 eeu-846 ie-75300-r-em users manual u11354e u11354j ep-753108gc/gk-r users manual eeu-1495 eeu-968 pg-1500 users manual eeu-1335 u11940j software ra75x assembler package operation eeu-1346 eeu-731 users manual language eeu-1363 eeu-730 pg-1500 controller users manual pc-9800 series eeu-1291 eeu-704 (ms-dos) base ibm pc series u10540e eeu-5008 (pc dos) base other related documents document name document no. english japanese ic package manual c10943x semiconductor device mounting technology manual c10535e c10535j quality grades on nec semiconductor devices c11531e c11531j nec semiconductor device reliability/quality control system c10983e c10983j electrostatic discharge (esd) test C mem-539 guide to quality assurance for semiconductor devices mei-1202 c11893j microcontroller-related product guide third partys product C u11416j caution the above related documents are subject to change without notice. for design purposes, etc., be sure to use the latest versions. 58 m pd75p3116 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. 59 m pd75p3116 nec electronics inc. (u.s.) santa clara, california tel: 800-366-9782 fax: 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. sao paulo-sp, brasil tel: 011-889-1680 fax: 011-889-1689 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j96. 8 60 m pd75p3116 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5 the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re- export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. qtop is a trademark of nec corporation. ms-dos is a trademark of microsoft corporation. ibm dos, pc/at, and pc dos are trademarks of international business machines corporation. |
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